The typical semiconductor memory device usually includes a large number of memory cells arranged into columns and rows to form one or more memory cell arrays. The memory cells of the same row are commonly coupled to a word line, while the memory cells of the same column are commonly coupled to a bit line (or pair of bit lines). For smaller capacity memory devices such conventional row and column arrangements allow adequate speed in accessing the data within the memory cells.
The increasing computing power and complexity of electronic systems has given rise to a demand for higher density and higher speed semiconductor memory devices. Conventional approaches that utilize one or more memory cell arrays, each having one set of word lines and bit lines, do not provide the compact size and rapid speed necessary to address the needs of more compact and powerful systems. One approach to improve a semiconductor memory device is to utilize "global" word lines. Semiconductor memory devices with global word lines will typically include a number of memory cell arrays, each with its own set of "local" word lines. Global word lines extend over groups of memory cell arrays, and are coupled to the local word lines of the arrays. Such arrangements allow for a row decoder circuit that is shared among multiple arrays, and thus provides for a more compact arrangement. Furthermore, the global word lines can be fabricated from a lower resistance material, improving the overall speed of the semiconductor memory device.
The memory cells within a high-density array are accessed according to various memory device operations. Such operations include read operations (common to nearly all memory devices), write operations (common to volatile memory devices), and program and erase operations (common to many nonvolatile memory devices). To access memory cells, an external memory address is applied which activates a word line within a predetermined group of arrays. When activated, the word line couples a row of memory cells to the bit lines of the array. A data input/output (I/O) path is then enabled between the bit lines of the array and a data amplifier circuit.
An example of a data access operation is set forth in FIG. 1A. FIG. 1A is a block schematic diagram that illustrates a portion of a semiconductor memory device. The portion is designated by the general reference character 100 and is shown to include four memory cell arrays (102a-102d). Each memory cell array includes a number of local word lines (not shown) that are coupled to global word lines common to all of the memory cell arrays (102a-102d). A group of local word lines may be coupled to each global word line by a local row driver circuit. Thus, when a global word line is activated, according to local decoding signals, one of the local word lines associated with the activated global word line will be selected.
Within FIG. 1A, a global word line is shown at item 104, and represents a global word line that has been activated by a row decoder circuit 106 in response to an applied address. Each memory cell array (102a-102d) further includes an associated set of even bit lines (108a-108d) and odd bit lines (110a-110d). Each set of even bit lines (108a-108d) is coupled to an associated even sense amplifier bank (112a-112d). In a similar fashion, each set of odd bit lines (110a-110d) is coupled to an associated odd sense amplifier bank (114a-114d). Each even and odd sense amplifier bank (112a-112d and 114a-114d) includes sense amplifiers and select gates (not shown). According to other address information, the select gates couple selected bit lines to even I/O lines 116 and to odd I/O lines 118. The even I/O lines 116 are coupled to a first data amplifier 120, and the odd I/O lines 118 are coupled to a second data amplifier 122.
In the particular prior art example of FIG. 1A, a data access to the memory cell 102b is illustrated. The resulting data path from memory cell array 102b to the data amplifiers (120 and 122) is illustrated by a dashed line. Thus, in the case of a read operation, the activated global word line 104 results in the activation of a local word line within memory cell array 102b. Data signals are placed on even bit line set 108b and odd bit line set 110b. Even and odd sense amplifier banks 112b and 114b are activated, placing amplified data signals on the even and odd I/O lines (116 and 118). The data signals on the I/O lines (116 and 118) are further amplified by the first and second data amplifiers (120 and 122).
Despite continuing advances in semiconductor integrated circuit manufacturing technology, in the course of fabricating a semiconductor memory device, manufacturing defects can give rise to nonfunctional memory cells within an array. In order to preserve the functionality of memory devices having such defects, redundant memory cells are often employed. Redundant memory cells are extra memory cells that are used to replace defective memory cells. A typical redundancy scheme includes row-wise redundancy, in which one or more extra rows of memory cells are created within a memory cell array, and column-wise redundancy, in which one or more extra columns of memory cells are created within the memory cell array.
In architectures utilizing global word lines, redundant global word lines can also be used. FIG. 1B sets forth an example of the architecture set forth in FIG. 1A in which a redundant global word line is used to replace a defective global word line 104'. In FIG. 1B, it is assumed that global word line 104' is defective (by a short, or the like). To avoid losing the functionality of all four memory cell arrays (102a-102d), a redundant global word line 124 is provided. It is understood that the redundant global word line 124 is coupled to a group of redundant local word lines within each memory cell array (102a-102d). In operation, the addresses corresponding to the defective global word line 104' are identified, and redundancy circuits enabled, so that the redundant global word line 124 will be activated in lieu of the defective global word line 104'. In this manner, the redundant global word line 124 is activated, and according to local address signals, a redundant local word line within memory cell array 102b is selected, coupling a row of redundant memory cells to the odd bit line set 108b and even bit line set 110b. The sense amplifier banks (112b and 114b), I/O lines (116 and 118), and data amplifiers (120 and 122) operate as previously described in conjunction with FIG. 1A.
A drawback to the redundancy arrangement of FIG. 1B can arise in the event the redundant global word line 124 is also defective. In such a case, all four memory cell arrays (102a-102d) can be rendered non-operational. While more redundant global word lines could be added, such an approach would require the addition of one more group of redundant local word lines to each of the memory cell arrays (102a-102d), undesirably adding to the overall size of the semiconductor memory device.
It would be desirable to arrive at a semiconductor memory device architecture that employs global word lines, but that does not suffer from the limited redundancy capabilities of the prior art. At the same time, such a memory device should remain compact and provide high-speed performance.